In advanced integrated circuit technologies, e-fuses have been implemented at the polycrystalline silicon (PC) level. During programming, a high current pulse of short duration can be passed through an e-fuse structure to irreversibly migrate silicide on top of the PC, causing a change in resistance and thus acting as a programmable fuse. However, as scaling continues to tighter pitch, it is becoming harder to implement e-fuses at the PC level for certain device integration schemes with high-k metal gate processes. As such, there is a drive to implement e-fuses at the metal interconnect levels (i.e., a back-end or “BEOL e-fuse”) and use the phenomenon of electromigration (EM) to program the fuses.
A conventional BEOL e-fuse structure includes via 124 connecting an upper line 122 and a lower line 112 as depicted in FIG. 1A. Line 122 can be connected to perform as the e-fuse anode and line 112 as the cathode, with electron flow from line 112 through via 124 to line 122. Via 124 can be a single via or a stacked via. There are several challenges with implementing a BEOL e-fuse. For one, programming the BEOL e-fuse can require more current than the PC e-fuse at least partly due to the fact that the liner materials used with copper interconnects, such as tantalum (Ta) and tantalum nitride (TaN), must be blown along with the copper in order to achieve proper fuse programming. US Patent Publication 2005/0285222 A1 by Thei et al. suggests to enable programming an e-fuse at lower current by intentionally misaligning via 224 relative to lower line 212 (or vs upper line 222 or both), as shown in FIG. 2A (depicting FIG. 14a of Thei et al). When offset by distance “D”, the contact area X at the via/line interface is reduced which theoretically concentrates current density at that interface. But this approach is not reliable since during processing the contact area can also extend vertically to include area Y (see FIG. 2B). This via offset design also makes the structure susceptible to current leakage to neighboring circuit elements thus lowering reliability and yield. Furthermore, such misalignment relative to the upper line 222 requires a single damascene process which adds to the cost of manufacturing.
In addition to requiring a relatively high programming current, a further problem with the conventional BEOL e-fuse is controlling the location of the void. Line-level features adjacent to the e-fuse elements can be quite close, such that when a programming surge through a BEOL e-fuse causes a void to open within line 122, an overlying cap layer (not shown) or dielectric 125 can be damaged, and that can enable current leakage to the adjacent line-level features. Having the void occur in via 124 would be preferred, and can be promoted by ensuring that the programming surge creates greater current density in the via than in other portions of the electrical path. One option is to design via 124 to have a smaller cross section than line 122, but at the tightest pitch levels, lithography is not capable of forming such a ‘smaller cross section via’ when the lines are made at the minimum lithographic dimension.
In state of the art integrated circuitry, the most advanced lithography available is used to form the semiconductor devices, as well as the lowest interconnect levels (e.g., “M1” and “M2”). The smallest wiring dimension (also referred to as the critical dimension or ‘CD’ or ‘groundrule’ dimension) that can be patterned lithographically correlates to the device dimensions made by that lithography. Table 1 shows the anticipated device gate length and corresponding wiring pitch at M1, according to the “International Technology Roadmap for Semiconductors, 2010 update”, hereby incorporated by reference.
TABLE 1INTC6 MPU Interconnect Technology RequirementsYear of Production201120122013201420152016Gate Length (nm)24.222.0920.1718.4116.8015.34M1 wiring pitch (nm)867261544843Barrier/cladding thickness2.92.62.42.11.91.7(for Cu M1 wiring) (nm)
The minimum or lithographic pitch, as shown in FIG. 1B (at least in the tightest pitch interconnect layers), is the sum of the minimum line width “W” (groundrule line width) and minimum spacing “S” (groundrule space) between adjacent features. A structure having a dimension smaller than half pitch shall be referred to herein as a “sub-lithographic” or “sub-groundrule” structure.
Various techniques have been proposed to form a sub-lithographic via, for example, U.S. Pat. No. 7,696,085 to Li et al. discloses a sub-lithographic via in a dual damascene metal interconnect structure formed by patterning a via opening at a standard dimension, then back filling the opening using self-assembling block copolymers (“SABC”). The deposition and patterning of the SABC adds process steps, complexity and expense.
Another technique is disclosed in “Fabrication of Nanoscale Vias by Offset Patterning”, by Chi Ho Lau and S. W. Ricky Lee (Proceedings of MicroNano08, Jun. 3-5, 2008, Hong Kong). According to this technique, a first via having standard photolithographic size is formed in a first dielectric layer according to a via mask. An etch stop and a second dielectric layer are then deposited. The second dielectric is patterned just as the first except the mask is offset. The via etched according to the intersection of the patterns has a reduced cross section. This process is undesirable since it requires two via patterning steps.
There remains a need for an inexpensive BEOL e-fuse that can be reliably programmed by electromigration that creates a void in the via.